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FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
پیاده سازی FPGA ماژول امنیتی IoT به صورت پویا قابل تنظیم با استفاده از الگوریتم جابجایی-2019 Internet of Things (IoT) is a promising technology that is continuously spreading around the world leading to
many challenges facing cryptographic designers who are trying to fulfill the security standards of IoT constrained
devices. In this work, a new design is proposed that adds a new dimension of security by using the concept of
frequency hopping to generate a pseudo-random pattern for switching between 5 lightweight cryptographic
ciphers: AEGIS, ASCON, COLM, Deoxys and OCB that are participating in the Competition for Authenticated
Encryption, Security, Applicability, and Robustness (CAESAR). The proposed design exploits the advantages
of Dynamic Partial Reconfiguration (DPR) technology in Field Programmable Gate Arrays (FPGAs) to switch
between the 5 ciphers using Internal Configuration Access Port controller (AXI-HWICAP) providing a decrease
of 58% and 80% in area utilization and power consumption respectively. The design is synthesized using Xilinx
Vivado 2015.2 and mounted on Zynq evaluation board (XC7Z020LG484-1). Keywords: CAESAR | FPGA | DPR | Cryptography | Hopping | AEAD | IoT |
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