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ردیف | عنوان | نوع |
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1 |
Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs
رمزگشاهای شبکه عصبی برای تصحیح خطای کوانتومی با استفاده از کدهای سطحی: کاوش فضایی مبادلات هزینه و عملکرد سخت افزار-2022 Quantum error correction (QEC) is required in quantum computers to mitigate the effect of
errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most
computationally expensive task in the classical electronic back-end. Decoders employing neural networks
(NN) are well-suited for this task but their hardware implementation has not been presented yet. This work
presents a space exploration of fully connected feed-forward NN decoders for small distance surface codes.
The goal is to optimize the NN for the high-decoding performance, while keeping a minimalistic hardware
implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We
demonstrate that hardware-based NN-decoders can achieve the high-decoding performance comparable to
other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (≈ 440 ns)
of current solid-state qubit technologies for both application-specific integrated circuit designs (<30 ns) and
field-programmable gate array implementations (<90 ns). These results indicate that NN-decoders are viable
candidates for further exploration of an integrated hardware implementation in future large-scale quantum
computers.
INDEX TERMS: Application-specific integrated circuit (ASIC) | complementary metal-oxide semiconductor (CMOS) | CMOS integrated circuits | combinational circuits | cryo-CMOS decoding | cryogenic electronics | digital integrated circuits, error correction codes | feedforward neural networks (NNs) | field programmable gate array (FPGA) | fixed-point arithmetic | machine learning NNs | pareto analysis | quantum computing | quantum-error-correction (QEC) codes | supervised learning, surface codes (SCs). |
مقاله انگلیسی |
2 |
Quantum Dimension Reduction for Pattern Recognition in High-Resolution Spatio-Spectral Data
کاهش ابعاد کوانتومی برای تشخیص الگو در داده های فضایی-طیفی با وضوح بالا-2022 The promises of advanced quantum computing technology have driven research in the simulation of quantum computers on
classical hardware, where the feasibility of quantum algorithms for real-world problems can be investigated. In domains such as High
Energy Physics (HEP) and Remote Sensing Hyperspectral Imagery, classical computing systems are held back by enormous readouts
of high-resolution data. Due to the multi-dimensionality of the readout data, processing and performing pattern recognition operations
for this enormous data are both computationally intensive and time-consuming. In this article, we propose a methodology that utilizes
Quantum Haar Transform (QHT) and a modified Grover’s search algorithm for time-efficient dimension reduction and dynamic pattern
recognition in data sets that are characterized by high spatial resolution and high dimensionality. QHT is performed on the data to
reduce its dimensionality at preserved spatial locality, while the modified Grover’s search algorithm is used to search for dynamically
changing multiple patterns in the reduced data set. By performing search operations on the reduced data set, processing overheads
are minimized. Moreover, quantum techniques produce results in less time than classical dimension reduction and search methods.
The feasibility of the proposed methodology is verified by emulating the quantum algorithms on classical hardware based on field
programmable gate arrays (FPGAs). We present designs of the quantum circuits for multi-dimensional QHT and multi-pattern Grover’s
search. We also present two emulation techniques and the corresponding hardware architectures for this methodology. A high
performance reconfigurable computer (HPRC) was used for the experimental evaluation, and high-resolution images were used as the
input data set. Analysis of the methods and implications of the experimental results are discussed.
Index Terms— Quantum computing | field-programmable gate arrays (FPGAs) |
مقاله انگلیسی |
3 |
Timing Constraints Imposed by Classical Digital Control Systems on Photonic Implementations of Measurement-Based Quantum Computing
محدودیت های زمانی اعمال شده توسط سیستم های کنترل دیجیتال کلاسیک بر پیاده سازی فوتونیک محاسبات کوانتومی مبتنی بر اندازه گیری-2022 Most of the architectural research on photonic implementations of measurement-based quantum computing (MBQC) has focused on the quantum resources involved in the problem with the implicit
assumption that these will provide the main constraints on system scaling. However, the “flying-qubit” architecture of photonic MBQC requires specific timing constraints that need to be met by the classical control
system. This classical control includes, for example, the amplification of the signals from single-photon
detectors to voltage levels compatible with digital systems; the implementation of a control system which
converts measurement outcomes into basis settings for measuring subsequent cluster qubits, in accordance
with the quantum algorithm being implemented; and the digital-to-analog converter and amplifier systems
required to set these measurement bases using a fast phase modulator. In this article, we analyze the digital
system needed to implement arbitrary one-qubit rotations and controlled-not gates in discrete-variable
photonic MBQC, in the presence of an ideal cluster state generator, with the main aim of understanding the
timing constraints imposed by the digital logic on the analog system and quantum hardware. We have verified
the design using functional simulations and have used static timing analysis of a Xilinx field-programmable
gate array (7 series) to provide a practical upper bound on the speed at which the adaptive measurement
processing can be performed, in turn constraining the photonic clock rate of the system. The design and
testing system is freely available for use as the basis of analysis of more complex designs, incorporating more
recent proposals for photonic quantum computing. Our work points to the importance of codesigning the
classical control system in tandem with the quantum system in order to meet the challenging specifications
of a photonic quantum computer.
INDEX TERMS: Field-programmable gate array (FPGA) | measurement and feed-forward | measurement based quantum computing (MBQC) | photonic quantum computing | timing analysis. |
مقاله انگلیسی |
4 |
Field-programmable gate arrays in a low power vision system
آرایه های دروازه ای قابل برنامه ریزی در یک سیستم دید کم قدرت-2021 In recent years, field-programmable gate arrays have played a major role in developing low power electronic systems. End users usually prefer systems with high performance, reduced size, and low power consumption. These requirements create a challenging task for designers. Re-configuring technology allows the use of field-programmable gate arrays to be at the maximum level during runtime. This paper proposes the implementation of the Dynamic Partial Reconfiguration technique to switch during runtime between two edge detection algorithms (FASTX and Sobel) in a computer vision algorithm. Xilinx Ultrascale+ZCU106 has been used as the implementation target since it consumes approximately 4% less power during runtime. It was discovered that the dynamic switching between algorithms reduces the on-chip area utilization. Finally, through experimental results our proposed work has demonstrated the applicability of computer vision with low power consumption. Keywords: Ultrascale | Low power | Computer vision application | Dynamic partial reconfiguration |
مقاله انگلیسی |
5 |
Action recognition of dance video learning based on embedded system and computer vision image
تشخیص عمل یادگیری ویدئویی رقص بر اساس سیستم تعبیه شده و تصویر بینایی ماشین-2021 Extraction and unfettered online / offline video sequence to identify complex human activity is computer vision a challenging task. To presents the classification of Indian classical dance moves using the powerful features of embedded system tools: Field Programmable Gate Array (FPGA). In this work, the Indian classical dance video for human action recognition is, YouTube data from offline and online control audio and video recordings of live performances carried out. Handprint create offline data with ten different themes familiar dance of 200 m / from various Indian classical dance forms in the context of a variety of poses. Online data collection dance ten different subjects from YouTube. Each dance posture is occupied 60 or video in both cases. FPGA training and 8 different sample dimensions, each performed by a plurality of sets of subject. The remaining two samples for testing the trained FPGA. Different FPGA architecture design, and with our test data in order to obtain better recognition accuracy. Compared the report on the same data set and other classification model to achieve a 90% recognition rate. Keywords: Field-programmable gate array (FPGA) | Learning action recognition | Embedded system tool |
مقاله انگلیسی |
6 |
A Survey and Taxonomy of FPGA-based Deep Learning Accelerators
مرور و طبقه بندی شتاب دهنده های یادگیری عمیق مبتنی بر FPGA-2019 Deep learning, the fastest growing segment of Artificial Neural Network (ANN), has led to the emergence of many machine learning applications and their implementation across multiple platforms such as CPUs, GPUs and recon- figurable hardware ( Field-Programmable Gate Arrays or FPGAs). However, inspired by the structure and function of ANNs, large-scale deep learning topologies require a considerable amount of parallel processing, memory re- sources, high throughput and significant processing power. Consequently, in the context of real time hardware systems, it is crucial to find the right trade-offbetween performance, energy efficiency, fast development, and cost. Although limited in size and resources, several approaches have showed that FPGAs provide a good starting point for the development of future deep learning implementation architectures. Through this paper, we briefly review recent work related to the implementation of deep learning algorithms in FPGAs. We will analyze and compare the design requirements and features of existing topologies to finally propose development strategies and implementation architectures for better use of FPGA-based deep learning topologies. In this context, we will examine the frameworks used in these studies, which will allow testing a lot of topologies to finally arrive at the best implementation alternatives in terms of performance and energy efficiency. Keywords: Deep learning | Framework | Optimized implementation | FPGA |
مقاله انگلیسی |
7 |
High-throughput and area-efficient fully-pipelined hashing cores using BRAM in FPGA
هسته های هش دار کاملاً پایپ شده با توان بالا و ناحیه-کارا با استفاده از BRAM در FPGA-2019 In this paper, an area-efficient fully-pipelined architecture of SHA-1 and SHA-256 implemented on FPGA is proposed for achieving high operating frequency and throughput. The conventional pipeline architec- ture consumes a lot of registers, especially the consumption increases dramatically for the higher number of pipeline stage. To solve this problem, a new scheme using block RAM (BRAM) is presented to reduce consumption of registers and make the fully-pipelined architecture simpler. Additionally, to achieve oper- ating frequency greater than 300 MHz, the new sub-cores of SHA-1 and SHA-256 combined with the loop unrolling and pre-computation techniques are introduced to the design. Compared to previous works, the throughput and throughput/Slice of SHA-1 and SHA-256 in proposed designs are substantially increased to 159.590 Gbps, 16.083 Mbps/slice and 154.880 Gbps, 10.94 Mbps/slice respectively on Kintex-7 FPGA. Keywords: field-programmable gate arrays (FPGA) | Cryptography | Secure Hash Algorithm (SHA) | Fully-pipelined | Block RAM (BRAM) |
مقاله انگلیسی |
8 |
VLSI implementation of reversible logic gates cryptography with LFSR key
پیاده سازی VLSI رمزنگاری دروازه های منطق برگشت پذیر با کلید LFSR-2019 The reversible computation is an emerging research field, which is used in different applications such as optical computing, digital signal processing, nanotechnologies, bio-information and in low-power com- putation. In present days, these applications require security algorithm to keep the information securely. The power and area analysis are one of the major challenges to mathematically secure cryptography pro- tocols. Moreover, hackers can take confidential data while it passes through the transmission line. To overcome this problem, Reversible logic cryptography design (RLCD) architecture is introduced in this pa- per. With the help of RLCD, the encryption and decryption architecture is designed. Linear feedback shift register (LFSR) is required to produce a key which is given to the encryption and decryption block. The application specified integrated chip (ASIC) and field-programmable gate array (FPGA) performances are evaluated for both existing and proposed method. More than 7% of the ASIC performances improved in RLCD-LFSR method compared to the conventional methods. Keywords: Application specified integrated chip | Field-programmable gate array | Linear feedback shift register | Power | Reversible logic cryptography design |
مقاله انگلیسی |
9 |
سازگاری یا مناسب بودن شتاب دهندههای سختافزاری اخیر (DSP ها، FPGA ها و GPU ها) برای بینایی ماشین و الگوریتم های پردازش تصویر
سال انتشار: 2018 - تعداد صفحات فایل pdf انگلیسی: 19 - تعداد صفحات فایل doc فارسی: 73 الگوریتم های بینایی کامپیوتری و پردازش تصویر، اجزای ضروری بسیاری از کاربردهای صنعتی، پزشکی، تجاری و تحقیقاتی را تشکیل میدهند. سیستمهای تصویربرداری مدرن تصاویر با وضوح بالا را در نرخهای فریم بالا فراهم میکنند و اغلب برای انجام محاسبات پیچیده برای پردازش دادههای تصویر مورد نیاز هستند. با این حال، در بسیاری از کاربردها پردازش سریع مورد نیاز است، یا به حداقل رساندن تاخیر برای نتایج تجزیه و تحلیل امری حائز اهمیت است. در این کاربردها، واحدهای پردازش مرکزی (CPU ها) ناکافی هستند، زیرا نمیتوانند محاسبات را با سرعت کافی انجام دهند. برای کاهش زمان محاسبه، الگوریتمها میتوانند در شتابدهندههای سختافزاری مانند پردازشگرهای سیگنال دیجیتال (DSPs)، آرایه های دریچهای برنامهپذیر میدانی (FPGA) و واحدهای پردازش گرافیکی (GPU ها) پیادهسازی شوند. با این حال، انتخاب یک شتابدهنده سختافزاری مناسب برای یک کاربرد خاص همواره چالش برانگیز بوده است. خانوادهها یا دسته های متعددی از DSP ها، FPGA ها و GPU ها در دسترس هستند و تفاوتهای فنی بین شتابدهندههای سختافزاری مختلف مقایسه را دشوار میسازد. همچنین مهم است که بدانیم چه سرعتی را می توان با استفاده از یک شتاب دهنده سختافزاری خاص برای یک الگوریتم خاص به دست آورد، زیرا انتخاب شتاب دهنده سختافزاری ممکن است هم به الگوریتم و هم به برنامه بستگی داشته باشد. جزییات فنی شتابدهندههای سختافزاری و عملکرد آنها در نشریات قبلی مورد بحث قرار گرفته است. با این حال، در بسیاری از این ارائهها محدودیتهایی وجود دارد، که، جزئیات فنی ناکافی برای فعال کردن انتخاب یک شتاب دهنده سختافزاری مناسب؛ مقایسه شتاب دهندههای سختافزاری در دو سطح فنآوری مختلف؛ و بحث در مورد تکنولوژیهای قدیمی از جمله این موارد هستند.
برای پرداختن به این مسائل، ما ملاحظات مهم را در زمان انتخاب شتاب دهندههای سختافزاری مناسب برای بینایی کامپیوتر و وظایف پردازش تصویر معرفی و بحث میکنیم و یک بررسی جامع از شتاب دهندههای سختافزاری ارائه میدهیم. ما در مورد جزئیات عملی ساختارهای تراشه، ابزارها و امکانات موجود، زمان توسعه و مزایا و معایب استفاده از DSPs، FPGA ها و GPU ها بحث خواهیم کرد. ما اطلاعات عملی در مورد جدیدترین DSP ها، FPGA ها و GPU ها و همچنین مثالهایی از مقالات ارائه میدهیم. هدف ما این است که توسعه دهندگان را قادر سازیم تا مقایسهای جامع بین شتاب دهندههای سختافزاری مختلف انجام دهند و یک شتاب دهندههای سختافزاری را انتخاب کنند که برای کاربرد خاص آنها بسیار مناسب باشد. کلمات کلیدی: مرور یا بازنگری | بینایی ماشین | پردازش تصویر | پردازشگر سیگنال دیجیتال (DSP) | آرایه دریچه ای برنامه پذیر میدانی (FPGA) | واحد پردازش گرافیکی (GPU) |
مقاله ترجمه شده |
10 |
Emulation-based fault analysis on RFID tags for robustness and security evaluation
تجزیه و تحلیل خطا مبتنی بر شبیه سازی بر RFID ارزیابی برچسب ها برای مقاومت و امنیت-2017 This paper presents an FPGA (field-programmable gate array) based fault emulation system for analysis of fault
impact on security and robustness of RFID (radio frequency identification) tags. This emulation system that deals
with any RFID protocol consists of two tag-reader pairs, a fault injection module and an emulation controller all
implemented in a single FPGA. The designed approach performs single event upset (SEU) and single event tran
sient (SET) fault injection and permits with high flexibility to set communication scenarios and related parame
ters. Moreover, we propose a classification of produced errors to evaluate fault impacts and identify most
sensitive tag flip-flops causing large number of failures and security concerns. The proposed fault injection ap
proach provides suitable means to increase tags security and robustness. In our experimentation campaign, an
ultra-high frequency (UHF) tag architecture has been exposed to intensive SEU and SET fault injections. The du
ration of the campaign including results analysis is 30 min in where 6,215,316 faults are experimented. Our re
sults have shown that the tag has tolerated 61.82% of SEUs and 67.83% of SETs. The flip-flops that constitute
the tag FSM (finite state machine) have been identified as the most sensitive parts causing large number of
failures.
Keywords: RFID tag | Fault injection | SEU emulation | FPGA platform | Robustness |
مقاله انگلیسی |