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ردیف | عنوان | نوع |
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1 |
Efficient Hardware Implementation of Finite Field Arithmetic AB + C for Binary Ring-LWE Based Post-Quantum Cryptography
اجرای سخت افزار کارآمد محاسبات میدان محدود AB + C برای رمزنگاری پس کوانتومی مبتنی بر حلقه باینری-LWE-2022 Post-quantum cryptography (PQC) has gained significant attention from the community
recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from
the well-developed quantum computers. The finite field arithmetic AB þ C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-
based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper,
we propose a novel hardware implementation of the finite field arithmetic AB þ C through three stages of interdependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware
architecture is then presented with detailed description; (iii) a thorough implementation has also been given
along with the comparison. Overall, (i) the proposed basic structure (u ¼ 1) outperforms the existing designs,
e.g., it involves 55.9% less area-delay product (ADP) than [13] for n ¼ 512; (ii) the proposed design also offers
very efficient performance in time-complexity and can be used in many future applications.
INDEX TERMS: Binary ring-learning-with-errors | finite field arithmetic | FPGA platform | hardware design | post-quantum cryptography |
مقاله انگلیسی |
2 |
Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs
رمزگشاهای شبکه عصبی برای تصحیح خطای کوانتومی با استفاده از کدهای سطحی: کاوش فضایی مبادلات هزینه و عملکرد سخت افزار-2022 Quantum error correction (QEC) is required in quantum computers to mitigate the effect of
errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most
computationally expensive task in the classical electronic back-end. Decoders employing neural networks
(NN) are well-suited for this task but their hardware implementation has not been presented yet. This work
presents a space exploration of fully connected feed-forward NN decoders for small distance surface codes.
The goal is to optimize the NN for the high-decoding performance, while keeping a minimalistic hardware
implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We
demonstrate that hardware-based NN-decoders can achieve the high-decoding performance comparable to
other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (≈ 440 ns)
of current solid-state qubit technologies for both application-specific integrated circuit designs (<30 ns) and
field-programmable gate array implementations (<90 ns). These results indicate that NN-decoders are viable
candidates for further exploration of an integrated hardware implementation in future large-scale quantum
computers.
INDEX TERMS: Application-specific integrated circuit (ASIC) | complementary metal-oxide semiconductor (CMOS) | CMOS integrated circuits | combinational circuits | cryo-CMOS decoding | cryogenic electronics | digital integrated circuits, error correction codes | feedforward neural networks (NNs) | field programmable gate array (FPGA) | fixed-point arithmetic | machine learning NNs | pareto analysis | quantum computing | quantum-error-correction (QEC) codes | supervised learning, surface codes (SCs). |
مقاله انگلیسی |
3 |
Quantum computing in power systems
محاسبات کوانتومی در سیستم های قدرت-2022 Electric power systems provide the backbone of modern industrial societies. Enabling scalable grid analytics is the keystone to
successfully operating large transmission and distribution systems. However, today’ s power systems are suffering from everincreasing computational burdens in sustaining the expanding communities and deep integration of renewable energy resources,
as well as managing huge volumes of data accordingly. These unprecedented challenges call for transformative analytics to support
the resilient operations of power systems. Recently, the explosive growth of quantum computing techniques has ignited new hopes
of revolutionizing power system computations. Quantum computing harnesses quantum mechanisms to solve traditionally
intractable computational problems, which may lead to ultra-scalable and efficient power grid analytics. This paper reviews the
newly emerging application of quantum computing techniques in power systems. We present a comprehensive overview of existing
quantum-engineered power analytics from different operation perspectives, including static analysis, transient analysis, stochastic
analysis, optimization, stability, and control. We thoroughly discuss the related quantum algorithms, their benefits and limitations,
hardware implementations, and recommended practices. We also review the quantum networking techniques to ensure secure
communication of power systems in the quantum era. Finally, we discuss challenges and future research directions. This paper will
hopefully stimulate increasing attention to the development of quantum-engineered smart grids.
keywords: Quantum computing | power system | variational quantum algorithms | quantum optimization | quantum machine learning | quantum security. |
مقاله انگلیسی |
4 |
Synchronization of Hindmarsh Rose Neurons
هماهنگ سازی از نورون های Hindmarsh Rose-2020 Modeling and implementation of biological neurons are key to the fundamental understanding of
neural network architectures in the brain and its cognitive behavior. Synchronization of neuronal
models play a significant role in neural signal processing as it is very difficult to identify the actual
interaction between neurons in living brain. Therefore, the synchronization study of these neuronal
architectures has received extensive attention from researchers. Higher biological accuracy of these
neuronal units demands more computational overhead and requires more hardware resources for
implementation. This paper presents a two coupled hardware implementation of Hindmarsh Rose
neuron model which is mathematically simpler model and yet mimics several behaviors of a real
biological neuron. These neurons are synchronized using an exponential function. The coupled system
shows several behaviors depending upon the parameters of HR model and coupling function. An
approximation of coupling function is also provided to reduce the hardware cost. Both simulations and
a low cost hardware implementations of exponential synaptic coupling function and its approximation
are carried out for comparison. Hardware implementation on field programmable gate array (FPGA)
of approximated coupling function shows that the coupled network produces different dynamical
behaviors with acceptable error. Hardware implementation shows that the approximated coupling
function has significantly lower implementation cost. A spiking neural network based on HR neuron
is also shown as a practical application of this coupled HR neural networks. The spiking network
successfully encodes and decodes a time varying input. Keywords: Computational neuroscience | Hindmarsh Rose neuron (HR) | Digital | Spiking Neural Networks (SNNs) | Field programmable gate arrays (FPGAs) | Nengo |
مقاله انگلیسی |
5 |
A low-cost and high-speed hardware implementation of spiking neural network
اجرای سخت افزار کم هزینه و پر سرعت شبکه عصبی اسپایک -2020 Spiking neural network (SNN) is a neuromorphic system based on the information process and store procedure of biological neurons. In this paper, a low-cost and high-speed implementation for a spiking neural network based on FPGA is proposed. The LIF (Leaky-Integrate–Fire) neuron model and tempotron supervised learning rules are used to construct the SNN which can be applied to the classification of pictures. A combined circuit instead of lookup table implementation method is proposed to realize the complex computing of kernel function in LIF neuron model. In addition, this work replaces the multi- plication operations in the weights training with the arithmetic shift, which can speed up the training efficiency and reduce the consumption of computing resources. Experimental results based on Vertix-7 FPGA shows that the classification accuracy is approximately 96% and the average time for classifying a sample is 0.576 us at the maximum frequency 178 MHz which achieves approximately 908,578 speedup compared with the software implementation on Matlab. Keywords: Spiking neural network | Neurons | Hardware implementation | Speed-up | Leaky-Integrate–Fire | Tempotron supervised learning rules |
مقاله انگلیسی |
6 |
A Digital Hardware Implementation of Spiking Neural Networks with Binary FORCE Training
اجرای سخت افزار دیجیتالی شبکه های عصبی اسپایک با آموزش باینری FORCE-2020 The brain, a network of spiking neurons, can learn complex dynamics by adapting its spontaneous chaotic
activity. One of the dominant approaches used to train such a network, the FORCE method, has recently
been applied to spiking neural networks. This method employs a pool of randomly connected spiking
neurons, called a reservoir, to create chaos and uses the recursive least square (RLS) method to change its
dynamic to what is required to follow a teacher signal. Here, we propose a digital hardware architecture for
spiking FORCE with some modifications to the original method. First, to reduce the memory usage in
hardware implementation, we show that careful binarization of the reservoir weights could preserve its
initial chaotic activity. Second, we generate the connection matrix on-the-fly instead of storing the whole
matrix. Third, a single processor systolic array implementation of the RLS using the inverse QR
decomposition is exploited to update the readout layer weights. This implementation is not only more
hardware-friendly but also more numerically stable in reduced precision than the standard RLS
implementation. Fourth, we implement the design in both single and custom-precision floating-point
number systems. Finally, we implement a network of 510 Izhikevic neurons on a Xilinx Artix-7 FPGA with
32, 24, and 18 bits floating-point numbers. To confirm the correctness of our architecture, we successfully
train our hardware using three different teacher signals. Keywords: FORCE learning | field programmable gate array (FPGA) | spiking neural network (SNN) | recursive least square (RLS) | QR decomposition | systolic array |
مقاله انگلیسی |
7 |
A simulated approach to evaluate side-channel attack countermeasures for the Advanced Encryption Standard
یک روش شبیه سازی شده برای ارزیابی اقدامات متقابل حمله کانال جانبی برای استاندارد رمزگذاری پیشرفته-2019 Modern networks have critical security needs and a suitable level of protection and performance is usually achieved with the use of dedicated hardware cryptographic cores. Although the Advanced Encryption Standard (AES) is considered the best approach when symmetric cryptography is required, one of its main weaknesses lies in its measurable power consumption. Side-Channel Attacks (SCAs) use this emitted power to analyse and revert the mathematical steps and extract the encryption key.
Nowadays they exist several dedicated equipment and workstations for SCA weaknesses analysis and the evaluation of the related countermeasures, but they can present significant drawbacks as a high cost for the instrumentation or, in case of cheaper instrumentation, the need to underclock the physical circuit implementing the AES cipher, in order to adapt the circuit clock frequency accordingly to the power sampling rate of ADCs or oscilloscopes bandwidth. In this work, we proposed a methodology for Correlation and Differential Power Analysis against hardware implementations of an AES core, relying only on a simulative approach. Our solution extracts simulated power traces from a gate-level netlist and then elaborates them using mathematical-statistical procedures. The main advantage of our solution is that it allows to emulate a real attack scenario based on emitted power analysis, without requiring any additional physical circuit or dedicated equipment for power samples acquisition, neither modifying the working conditions of the target application context (such as the circuit clock frequency). Thus, our approach can be used to validate and benchmark any SCA countermeasure during an early step of the design, thereby shortening and helping the designers to find the best solution during a preliminary phase and potentially without additional costs. |
مقاله انگلیسی |
8 |
Pseudorandom number generator based on enhanced Hénon map and its implementation
مولد عدد شبه تصادفی بر اساس نگاشت Hénon افزایش یافته و پیاده سازی آن-2019 This paper presents a pseudorandom number generator (PRNG) based on enhanced Hénon map (EHM)
and its implementation in software and hardware for chaos-based cryptosystems with high processing
such as image or video encryption. The proposed EHM presents better statistical properties and higher
key sensitivity in comparison with classic Hénon map (CHM) by means of numerical tests such as bifurcation
diagrams, largest Lyapunov exponent, Gottwald-Melbourne test, and histograms. The proposed 8-
bit PRNG-EHM algorithm is implemented in MATLAB (software) and in FPGA technology (hardware) for
experimental results. In hardware implementation, we use VHDL language and the Altera DE2-115 FPGA
board with RS-232 serial port communication for data extraction, which are analyzed with MATLAB. In
both software and hardware level, the proposed PRNG-EHM passes the randomness NIST 800-22 statistical
tests. For first time in literature, a comprehensive security analysis from a cryptographic point of
view is presented for hardware implementation such as key space analysis, key sensitivity, floating frequency,
histograms, autocorrelation, correlation, entropy, and performance. Comparisons of proposed
PRNG-EHM with recent similar schemes show main advantages in security capabilities for cryptographic
applications. According with the results, the proposed scheme can be used in chaos-based cryptographic
applications at software or hardware implementation. Keywords: Chaos | Pseudorandom number generator | Security analysis | Hardware implementation |
مقاله انگلیسی |
9 |
An area-efficient bit-serial sequential polynomial basis finite field GF(2m) multiplier
An area-efficient bit-serial sequential polynomial basis finite field GF(2m) multiplier-2019 Many cryptographic and error control coding algorithms rely on finite field arithmetic. Hardware
implementation of these algorithms requires an efficient realization of finite field GF(2m) arithmetic
operations. Finite field multiplication is complex among the basic arithmetic operations, and it is
employed in field exponentiation and inversion operations. Various algorithms and architectures are
proposed in the literature for hardware implementation of finite field multiplication to achieve a
reduction in area and delay. In this paper, a modified interleaved modular reduction multiplication
algorithm and its bit-serial sequential architecture are proposed. It is observed from the comparison of
analytical results that the proposed architecture achieves the reduction in area and area-delay product
compared to the existing multipliers. The proposed multiplier achieves an improvement of 39% in area
and 17% in area-delay product estimations for field order of 409 when compared with the best sequential
multiplier available in the literature. Application specific integrated circuit (ASIC) implementation of the
proposed multiplier together with the two most comparable multipliers confirms that the proposed
multiplier outperforms in terms of area and area-delay product. The proposed multiplier is suitable for
implementation of security in Internet of Things (IoT) gateways and edge-devices. Keywords: Finite field arithmetic | Polynomial basis | Bit-serial multiplier | Elliptic curve cryptography | Internet of Things (IoT) |
مقاله انگلیسی |
10 |
Improved triangular-based star pattern recognition algorithm for low-cost star trackers
الگوریتم تشخیص الگوی ستاره ای مبتنی بر مثلث بهبود یافته برای ردیاب های ستاره کم هزینه-2019 Star identification algorithms based on triangular-pattern are more suitable for low-cost star trackers
since they require less star density in the field of view to operate effectively. In this paper, we propose
a modified star pattern recognition algorithm based on the triangular-based algorithm of ‘‘LIEBE”. The
main contribution of the proposed work is twofold. First, a new strategy for the selection of star triplets
is proposed for database construction. Second, new selection criteria of the reference star are considered
for pattern generation process. A sky simulation program is developed to assess mainly the robustness
against different conditions of noise. The obtained results show an improvement in the overall identification
rate, more robustness towards missing stars, and more efficiency towards magnitude noise.
Furthermore, our proposed algorithm shows comparable robustness with the recently proposed triangular
algorithms despite their reliance on more accurate camera and a validation process. To assess the
algorithm performance, the algorithm is implemented on a prototype of Data Processing Unit (DPU)
based on ARM Cortex-M4 processor. In this part, we discuss the major design decisions and we present
the hardware architecture of DPU. The algorithm shows promising running time at a reduced on-board
database when implemented on ARM platform. Keywords: Star identification | Star pattern recognition | Star database optimization | Star tracker | Hardware implementation | Small satellite |
مقاله انگلیسی |