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نتیجه جستجو - VLSI Design

تعداد مقالات یافته شده: 2
ردیف عنوان نوع
1 Design and leakage assessment of side channel attack resistant binary edwards Elliptic Curve digital signature algorithm architectures
طراحی و ارزیابی نشت کانالهای جانبی معماری الگوریتم امضای دیجیتالی edwards Elliptic منحنی مقاوم در برابر حمله کانال-2019
Considering that Elliptic Curve Digital Signature Algorithm (ECDSA) implementations need to be efficient, flexible and Side Channel Attack (SCA) resistant, in this paper, a design approach and architecture for ECDSA and the underlined scalar multiplication operation is proposed for GF (2 k ), satisfying the above three directives. To achieve that, in the paper, Binary Edwards Curves (BECs) are adopted as an alter- native to traditional Weierstrass Elliptic Curves (ECs) for GF (2 k ) since they offer intrinsic SCA resistance against simple attacks due to their uniformity, operation regularity and completeness. To achieve high performance and flexibility, we propose a hardware/software ECDSA codesign approach where scalar mul- tiplication is implemented in hardware and integrated in the ECDSA functionality through appropriate drivers of an ECDSA software stack. To increase BEC scalar multiplier performance and introduce SCA resistance we adopt and expand a parallelism design strategy/methodology where GF (2 k ) operations of a scalar multiplier round for both point operations performed in this round are reordered and assigned into parallelism layer in order to be executed concurrently. Within this strategy we include hardware and software based SCA countermeasures that rely on masking/randomization and hiding. While scalar randomization is realized by the ECDSA software stack in an easy way, in order to achieve resistance us- ing hardware means, we propose and introduce in every scalar multiplier round, within the parallelism layers, projective coordinates randomization of all the round’s output points. So, in our approach, con- sidering that with the proposed parallelism plan in every scalar multiplier round BEC point operations are performed in parallel and that the round’s output points are randomized with a different number in each round, we manage to achieve maximum SCA resistance. To validate this resistance, we introduce and realize a leakage assessment process on BEC scalar multipliers for the first time in research literature. This process is based on real measurements collected from a controlled SAKURA X environment with a GF (2 233 ) based scalar multiplier implementation. Using Welch’s t -test we investigate possible information leakage of the multiplier’s input point and scalar and after an extended analysis we find trivial leakage. Finally, we validate the ECDSA architecture and its scalar multiplier efficiency by implementing it on a Zynq 70 0 0 series FPGA Avnet Zedboard and collecting very promising, well balanced, results on speed and hardware resources in comparison with other works.
Keywords: VLSI Design | Side channel attacks | Elliptic Curve cryptography | Hardware security
مقاله انگلیسی
2 A CAD approach for pre-layout optimal PDN design and its post-layout verification
یک روش CAD برای طراحی بهینه PDN قبل از طرح و تأیید پس از طرح آن-2019
Design of power distribution network (PDN) draws great attention to integrated circuit (IC) designers as it directly affects the circuit performance. The challenge is to immune the circuit from the noise arising due to PDN by means of effective placement of decoupling capacitance (decap) with optimal power, delay, energy and area utilization. Our work involves extraction of circuit parameters in the pre-layout stage and estimating decoupling capacitance as an early prediction activity based on dynamic power dissipation. We propose a new modular pre-layout PDN (MPLPDN) design approach, which modularizes the circuit and involves a computer aided design (CAD) methodology to investigate the changes in noise, power and delay parameter based on predictive decap allocation across the modules. A pruning methodology has been adopted to choose the best combination of the modules. The modularization algorithm is applied in a bottom up approach i.e. the lower level modules are combined at first and the top level module is created at the last stage. The experimental results based on pre and post layout simulation of application circuits show that MPLPDN achieves a considerable PDN noise suppression with a negligible increase in power, delay, energy and area. The comparison between pre-layout and post-layout simulation results also establishes the correctness of our early prediction.
Keywords: Low power VLSI design | Power distribution network (PDN) | Cryptographic algorithm | Digital signal processing (DSP) algorithm | Decoupling capacitance (decap) | Computer aided design (CAD) | Application specific integrated circuit (ASIC)
مقاله انگلیسی
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بازدید امروز: 5966 :::::::: بازدید دیروز: 3097 :::::::: بازدید کل: 40233 :::::::: افراد آنلاین: 53