با سلام خدمت کاربران در صورتی که با خطای سیستم پرداخت بانکی مواجه شدید از طریق کارت به کارت (6037997535328901 بانک ملی ناصر خنجری ) مقاله خود را دریافت کنید (تا مشکل رفع گردد).
ردیف | عنوان | نوع |
---|---|---|
1 |
System-level Power Integrity Optimization Based on High-Density Capacitors for enabling HPC/AI applications
بهینه سازی یکپارچگی قدرت در سطح سیستم مبتنی بر خازن های با چگالی بالا برای فعال کردن برنامه های HPC / AI-2020 In this work, we introduce platform-level power
integrity (PI) solutions to enable high-power core IPs and highbandwidth
memory (HBM) interface for HPC/AI applications.
High-complexity design methodology becomes more significant
to enable high-power operations of CPU/GPU/NPU that
preforms iteratively tremendous computing processes. In order
to achieve high-power performance at larger than 200W class,
system-level PI analysis and design guide at early design stage
is required to prevent drastic voltage variations at the bump
under comprehensive environments including SoC, interposer,
package and board characteristics. PI solutions based on highdensity
on-die capacitors are suitable for mitigating voltage
fluctuations by supplying quickly stored charges to silicon
devices. In adopting 2-/3-plate metal-insulator-metal (MIM)
capacitor with approximately 20nF/mm2 and 40nF/mm2, and
integrated stacked capacitor (ISC) with approximately
300nF/mm2, it is demonstrated that voltage properties (drop
and ripple) are able to be improved by system-level design
optimization such as power delivery network (PDN) design and
RTL-architecture manipulation. Consequently, system-level PI
solutions based on high-density capacitor are anticipated to
contribute to improving target performance of high-power
products in response to customer’s expectation for HPC/AI
applications. Keywords: HPC/AI | high-power applications | power integrity | power delivery network | decoupling capacitor | systemlevel design optimization |
مقاله انگلیسی |