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ردیف | عنوان | نوع |
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1 |
Deployment-Ready Quantum Key Distribution Over a Classical Network Infrastructure in Padua
توزیع کلید کوانتومی آماده استقرار بر روی یک زیرساخت شبکه کلاسیک در پادوآ-2022 Current technological progress is driving Quantum
Key Distribution towards a commercial and worldwide scale
expansion. Its capability to deliver secure communication
regardless of the computational power of the attackers will be a
fundamental feature in the next generations of telecommunication
networks. Nevertheless, demonstrations of QKD implementation in a real operating scenario and their coexistence with the
classical telecom infrastructure are of fundamental importance
for reliable exploitation. Here we present a Quantum Key
Distribution application implemented over a classical fiber-based
infrastructure. We exploit a 50 MHz source at 1550 nm, a single 13
km-long fiber cable for both the quantum and the classical channel,
and a simplified receiver scheme with just one single-photon
detector. In this way, we achieve an error rate of approximately
2% and a secret key rate of about 1.7 kbps, thus demonstrating the
feasibility of low-cost and ready-to-use Quantum Key Distribution
systems compatible with standard classical infrastructure.
Index Terms: Classical channel | cryptography | fiber, FPGA | padua | POGNAC | quantum communication | quantum key distribution | qubit4sync | telecommunication. |
مقاله انگلیسی |
2 |
Efficient Hardware Implementation of Finite Field Arithmetic AB + C for Binary Ring-LWE Based Post-Quantum Cryptography
اجرای سخت افزار کارآمد محاسبات میدان محدود AB + C برای رمزنگاری پس کوانتومی مبتنی بر حلقه باینری-LWE-2022 Post-quantum cryptography (PQC) has gained significant attention from the community
recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from
the well-developed quantum computers. The finite field arithmetic AB þ C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-
based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper,
we propose a novel hardware implementation of the finite field arithmetic AB þ C through three stages of interdependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware
architecture is then presented with detailed description; (iii) a thorough implementation has also been given
along with the comparison. Overall, (i) the proposed basic structure (u ¼ 1) outperforms the existing designs,
e.g., it involves 55.9% less area-delay product (ADP) than [13] for n ¼ 512; (ii) the proposed design also offers
very efficient performance in time-complexity and can be used in many future applications.
INDEX TERMS: Binary ring-learning-with-errors | finite field arithmetic | FPGA platform | hardware design | post-quantum cryptography |
مقاله انگلیسی |
3 |
Deep convolutional neural networks-based Hardware–Software on-chip system for computer vision application
سیستم سختافزار-نرمافزار روی تراشه مبتنی بر شبکههای عصبی عمیق برای کاربرد بینایی ماشین-2022 Embedded vision systems are the best solutions for high-performance and lightning-fast inspection tasks. As everyday life evolves, it becomes almost imperative to harness artificial
intelligence (AI) in vision applications that make these systems intelligent and able to make
decisions close to or similar to humans. In this context, the AI’s integration on embedded
systems poses many challenges, given that its performance depends on data volume and
quality they assimilate to learn and improve. This returns to the energy consumption and
cost constraints of the FPGA-SoC that have limited processing, memory, and communication
capacity. Despite this, the AI algorithm implementation on embedded systems can drastically
reduce energy consumption and processing times, while reducing the costs and risks associated
with data transmission. Therefore, its efficiency and reliability always depend on the designed
prototypes. Within this range, this work proposes two different designs for the Traffic Sign
Recognition (TSR) application based on the convolutional neural network (CNN) model,
followed by three implantations on PYNQ-Z1. Firstly, we propose to implement the CNN-based
TSR application on the PYNQ-Z1 processor. Considering its runtime result of around 3.55 s,
there is room for improvement using programmable logic (PL) and processing system (PS) in a
hybrid architecture. Therefore, we propose a streaming architecture, in which the CNN layers
will be accelerated to provide a hardware accelerator for each layer where direct memory
access (DMA) interface is used. Thus, we noticed efficient power consumption, decreased
hardware cost, and execution time optimization of 2.13 s, but, there was still room for design
optimizations. Finally, we propose a second co-design, in which the CNN will be accelerated
to be a single computation engine where BRAM interface is used. The implementation results
prove that our proposed embedded TSR design achieves the best performances compared to the
first proposed architectures, in terms of execution time of about 0.03 s, computation roof of
about 36.6 GFLOPS, and bandwidth roof of about 3.2 GByte/s.
keywords: CNN | FPGA | Acceleration | Co-design | PYNQ-Z1 |
مقاله انگلیسی |
4 |
Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs
رمزگشاهای شبکه عصبی برای تصحیح خطای کوانتومی با استفاده از کدهای سطحی: کاوش فضایی مبادلات هزینه و عملکرد سخت افزار-2022 Quantum error correction (QEC) is required in quantum computers to mitigate the effect of
errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most
computationally expensive task in the classical electronic back-end. Decoders employing neural networks
(NN) are well-suited for this task but their hardware implementation has not been presented yet. This work
presents a space exploration of fully connected feed-forward NN decoders for small distance surface codes.
The goal is to optimize the NN for the high-decoding performance, while keeping a minimalistic hardware
implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We
demonstrate that hardware-based NN-decoders can achieve the high-decoding performance comparable to
other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (≈ 440 ns)
of current solid-state qubit technologies for both application-specific integrated circuit designs (<30 ns) and
field-programmable gate array implementations (<90 ns). These results indicate that NN-decoders are viable
candidates for further exploration of an integrated hardware implementation in future large-scale quantum
computers.
INDEX TERMS: Application-specific integrated circuit (ASIC) | complementary metal-oxide semiconductor (CMOS) | CMOS integrated circuits | combinational circuits | cryo-CMOS decoding | cryogenic electronics | digital integrated circuits, error correction codes | feedforward neural networks (NNs) | field programmable gate array (FPGA) | fixed-point arithmetic | machine learning NNs | pareto analysis | quantum computing | quantum-error-correction (QEC) codes | supervised learning, surface codes (SCs). |
مقاله انگلیسی |
5 |
Quantum Dimension Reduction for Pattern Recognition in High-Resolution Spatio-Spectral Data
کاهش ابعاد کوانتومی برای تشخیص الگو در داده های فضایی-طیفی با وضوح بالا-2022 The promises of advanced quantum computing technology have driven research in the simulation of quantum computers on
classical hardware, where the feasibility of quantum algorithms for real-world problems can be investigated. In domains such as High
Energy Physics (HEP) and Remote Sensing Hyperspectral Imagery, classical computing systems are held back by enormous readouts
of high-resolution data. Due to the multi-dimensionality of the readout data, processing and performing pattern recognition operations
for this enormous data are both computationally intensive and time-consuming. In this article, we propose a methodology that utilizes
Quantum Haar Transform (QHT) and a modified Grover’s search algorithm for time-efficient dimension reduction and dynamic pattern
recognition in data sets that are characterized by high spatial resolution and high dimensionality. QHT is performed on the data to
reduce its dimensionality at preserved spatial locality, while the modified Grover’s search algorithm is used to search for dynamically
changing multiple patterns in the reduced data set. By performing search operations on the reduced data set, processing overheads
are minimized. Moreover, quantum techniques produce results in less time than classical dimension reduction and search methods.
The feasibility of the proposed methodology is verified by emulating the quantum algorithms on classical hardware based on field
programmable gate arrays (FPGAs). We present designs of the quantum circuits for multi-dimensional QHT and multi-pattern Grover’s
search. We also present two emulation techniques and the corresponding hardware architectures for this methodology. A high
performance reconfigurable computer (HPRC) was used for the experimental evaluation, and high-resolution images were used as the
input data set. Analysis of the methods and implications of the experimental results are discussed.
Index Terms— Quantum computing | field-programmable gate arrays (FPGAs) |
مقاله انگلیسی |
6 |
The “Cyber Security via Determinism” Paradigm for a Quantum Safe Zero Trust Deterministic Internet of Things (IoT)
پارادایم «امنیت سایبری از طریق جبرگرایی» برای اینترنت اشیا قطعی (IoT) ایمن صفر کوانتومی-2022 The next-generation Internet of Things (IoT) will control the critical infrastructure of the 21st
century, including the Smart Power Grid and Smart Cities. It will also support Deterministic Communications, where ‘deterministic traffic flows’ (D-flows) receive strict Quality-of-Service (QoS) guarantees.
A ‘Cybersecurity via Determinism’ paradigm for the next-generation ‘Industrial and Tactile Deterministic
IoT’ is presented. A forwarding sub-layer of simple and secure ‘deterministic packet switches’ (D-switches)
is introduced into layer-3. This sub-layer supports many deterministic Software Defined Wide Area Networks
(SD-WANs), along with 3 new tools for improving cyber security: Access Control, Rate Control, and
Isolation Control. A Software Defined Networking (SDN) control-plane configures each D-switch (ie FPGA)
with multiple deterministic schedules to support D-flows. The SDN control-plane can embed millions of
isolated Deterministic Virtual Private Networks (DVPNs) into layer 3. This paradigm offers several benefits:
1) All congestion, interference, and Distributed Denial-of-Service (DDOS) attacks are removed; 2) Buffer
sizes in D-switches are reduced by 1000C times; 3) End-to-end IoT delays can be reduced to ultra-low
latencies, i.e., the speed-of-light in fiber; 4) The D-switches do not require Gigabytes of memory to store
large IP routing tables; 5) Hardware support is provided in layer 3 for the US NIST Zero Trust Architecture;
6) Packets within a DVPN can be entirely encrypted using Quantum Safe encryption, which is impervious
to attacks by Quantum Computers using existing quantum algorithms; 7) The probability of an undetected
cyberattack targeting a DVPN can be made arbitrarily small by using long Quantum Safe encryption keys;
and 8) Savings can reach $10s of Billions per year, through reduced capital, energy and operational costs.
INDEX TERMS: Cyber security | deterministic, the Internet of Things (IoT) | quantum computing, zero trust | encryption | privacy | Software Defined Networking (SDN) | industrial internet of things (IIoT) | tactile Internet of Things | FPGA | Industry 4.0 | deterministic Internet of Things. |
مقاله انگلیسی |
7 |
Timing Constraints Imposed by Classical Digital Control Systems on Photonic Implementations of Measurement-Based Quantum Computing
محدودیت های زمانی اعمال شده توسط سیستم های کنترل دیجیتال کلاسیک بر پیاده سازی فوتونیک محاسبات کوانتومی مبتنی بر اندازه گیری-2022 Most of the architectural research on photonic implementations of measurement-based quantum computing (MBQC) has focused on the quantum resources involved in the problem with the implicit
assumption that these will provide the main constraints on system scaling. However, the “flying-qubit” architecture of photonic MBQC requires specific timing constraints that need to be met by the classical control
system. This classical control includes, for example, the amplification of the signals from single-photon
detectors to voltage levels compatible with digital systems; the implementation of a control system which
converts measurement outcomes into basis settings for measuring subsequent cluster qubits, in accordance
with the quantum algorithm being implemented; and the digital-to-analog converter and amplifier systems
required to set these measurement bases using a fast phase modulator. In this article, we analyze the digital
system needed to implement arbitrary one-qubit rotations and controlled-not gates in discrete-variable
photonic MBQC, in the presence of an ideal cluster state generator, with the main aim of understanding the
timing constraints imposed by the digital logic on the analog system and quantum hardware. We have verified
the design using functional simulations and have used static timing analysis of a Xilinx field-programmable
gate array (7 series) to provide a practical upper bound on the speed at which the adaptive measurement
processing can be performed, in turn constraining the photonic clock rate of the system. The design and
testing system is freely available for use as the basis of analysis of more complex designs, incorporating more
recent proposals for photonic quantum computing. Our work points to the importance of codesigning the
classical control system in tandem with the quantum system in order to meet the challenging specifications
of a photonic quantum computer.
INDEX TERMS: Field-programmable gate array (FPGA) | measurement and feed-forward | measurement based quantum computing (MBQC) | photonic quantum computing | timing analysis. |
مقاله انگلیسی |
8 |
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory
شبیه ساز مقیاس پذیر برای تبدیل فوریه کوانتومی با استفاده از چند FPGA با حافظه با پهنای باند بالا-2022 Quantum computing is regarded as the future of computing that hopefully provides exponentially large processing power compared to the conventional digital computing. However, current quantum
computers do not have the capability to correct errors caused by environmental noise, so that it is difficult
to run useful algorithms that require deep quantum circuits. Therefore, emulation of quantum circuits in
digital computers is essential. However, emulation of large quantum circuits requires enormous amount of
computations, and leads to a very large processing time. To reduce the processing time, we propose an FPGA
emulator with high-bandwidth-memory to emulate quantum Fourier transform (QFT), which is a major
part of many quantum algorithms. The proposed FPGA emulator is scalable in terms of both processing
speed and the number of qubits, and extendable to multiple FPGAs. We performed QFT emulations up
to 30 qubits using two FPGAs. According to the measured results, we have achieved 23:6 ∼ 24:5 times
speed-up compared to a fully optimized 24-core CPU emulator.
INDEX TERMS: Quantum computing | quantum circuits | high-bandwidth memory | FPGA | quantum Fourier transform. |
مقاله انگلیسی |
9 |
A high performance real-time vision system for curved surface inspection
یک سیستم دید در زمان واقعی با عملکرد بالا برای بازرسی سطح منحنی-2021 Surface quality plays an important role in inspection lines. In this paper, a novel imaging device combined with FPGA (Field Programmable Gate Array) based processing platform had been designed to detect and analyze curved surface defects for vision inspection. The optical imaging part was made by an optical device which can be used to collect curved surface features without anamorphous and a camera with 70k Hz linear CMOS was used to capture surface information. The FPGA based inspection platform had been developed for camera control and image processing. Inspecting experiments had been tested with an inspection accuracy of 0.2 mm x 0.2 mm which satisfied a 12 m/s real-time vision inspection line. This research result can be subsequently applied to various surface inspection scenarios. Keywords: Optical imaging | Curved surface inspection | Vision system | Image processing |
مقاله انگلیسی |
10 |
Dynamic 3D image simulation of basketball movement based on embedded system and computer vision
شبیه سازی تصویر پویا سه بعدی حرکت بسکتبال بر اساس سیستم تعبیه شده و بینایی ماشین-2021 Traditional empirical basketball teaching methods can be repeated, affecting serious basketball training efficiency and the acquisition of technical essentials. Based on this problem, the basketball training reproduction framework is built utilizing augmented reality innovation. The framework sets up a virtual reenactment model ofa ballplayer planning a player’s track. Simultaneously, as a helping player, it captures the basketball player’sactual situation, compares them with the simulated trajectories, and provides more targeted training. Based on virtual reality-based Virtual Data Augmentation Technology (VDRT), basketball technology’s teaching mode allows players to acquire key points of sports skills and significantly improve basketball players’ training efficiency as soon as possible. With the quick improvement of current science and innovation, for example, center, science and innovation, and electronic data innovation, more educational activities are being applied. However, modern educational methods’ important content is to master and use modern educational equipment and processes. This article uses basic concepts, characteristics, and virtual reality techniques and literature and information methods to explain the types of role play in basketball lessons. Finally, it analyzes the application programs of basketball theory education, technical education, tactical instruction and educational competitions that provide scientific standards for future basketball education reform. Keywords: Basketball movement | virtual data reinforcement technique (VDRT) | Field Programmable Gate Array (FPGA) |
مقاله انگلیسی |