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VLSI implementation of reversible logic gates cryptography with LFSR key
پیاده سازی VLSI رمزنگاری دروازه های منطق برگشت پذیر با کلید LFSR-2019 The reversible computation is an emerging research field, which is used in different applications such as optical computing, digital signal processing, nanotechnologies, bio-information and in low-power com- putation. In present days, these applications require security algorithm to keep the information securely. The power and area analysis are one of the major challenges to mathematically secure cryptography pro- tocols. Moreover, hackers can take confidential data while it passes through the transmission line. To overcome this problem, Reversible logic cryptography design (RLCD) architecture is introduced in this pa- per. With the help of RLCD, the encryption and decryption architecture is designed. Linear feedback shift register (LFSR) is required to produce a key which is given to the encryption and decryption block. The application specified integrated chip (ASIC) and field-programmable gate array (FPGA) performances are evaluated for both existing and proposed method. More than 7% of the ASIC performances improved in RLCD-LFSR method compared to the conventional methods. Keywords: Application specified integrated chip | Field-programmable gate array | Linear feedback shift register | Power | Reversible logic cryptography design |
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