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A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor
تجزیه و تحلیل قدرت متعادل حمله منطق بی دررو انعطاف پذیر با استفاده از تک ترانزیستور به اشتراک گذاری شارژ-2019 The existing Power Analysis Attacks (PAA) resilient adiabatic logic designs exhibit variations in current peaks,
have asymmetric structures and suffer from Non-Adiabatic Losses (NAL) during the evaluation phase of the
power-clock. However, asymmetric structure and variations in current peaks make the circuit susceptible to
PAA. In this paper, we present a novel PAA resilient adiabatic logic which has a symmetric structure, completely
removes NAL from the evaluation phase of the power-clock and exhibits minimal variations in current peaks for
gates as well as in an 8-bit Montgomery multiplier. The proposed logic has been compared with three existing
secure adiabatic logic designs for operating frequencies ranging from 1 MHz to 100 MHz and power-clock scaling
ranging from 1.8 V to 0.6 V. Simulation results of the gates show that our proposed logic exhibits the lowest
Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) at the frequencies mentioned
above. In addition, all the 2-input gates using proposed logic dissipate average energy within 0.3% of each other
and thus, lowest value of standard deviation at all the simulated frequencies. The simulation results for the 8-bit
Montgomery multiplier show that proposed logic exhibits the least value of NED and NSD at all the simulated
frequencies and under power-supply scaling. Keywords: Cryptography | Charge-sharing | Current consumption | Quasi-adiabatic logic | Power analysis attack | Secure |
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